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PRELIMINARY
Z89303/05/07 CPS DC-4222-03
PRELIMINARY CUSTOMERPROCUREMENTSPECIFICATION
Z89303/05/07
DIGITALTELEVISIONCONTROLLER
GENERAL DESCRIPTION
The Z89303/05/07 Digital Television Controllers are application-specific controllers designed to provide complete audio and video control of television receivers, video recorders, with advanced on-screen display facilities. The Z89303/05/07 are 24K, 16K and 12K ROM versions in 52-pin SDIP packages. The powerful 12 MHz Z89C00 RISC processor core allows the user to control the onboard peripheral functions and registers using the standard processor instruction set. The extensive character attributes can be controlled in two modes: by the on-screen display controller character control mode for maximum display control flexibility, and closed caption mode for optimum display of closed caption text. Closed caption text can be decoded directly from the composite video signal with the assistance of the processor's digital signal processing capabilities and displayed on the screen. The character representation in this mode allows for a simple attribute control through the insertion of control characters, and each word of RAM specifies two displayed characters. The character control mode provides access to the full set of attribute controls. Each word of RAM specifies a single displayed character and basic character attributes, allowing the modification of attributes on a character-by-character basis. The insertion of control characters permits direction of other character attributes. The fully customized 512 character set, formatted in two 256 character banks, can be displayed with a host of display attributes that incude underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency. The 16-bit display character representation allows the modification of some key attributes on a character-by-character basis. A character's pixel array is stored as a 16- or 18-word representation in Character Graphics ROM (CGROM). The ROM contents are referenced by a 16-bit word stored in video RAM (VRAM) defining the character type and its key attributes. Serial interfacing with the television tuner is provided through the tuner serial port. Other serial devices, such as digital channel tunning adjustments, may be accessed through the industry standard I2C port. Additional hardware provides the capability to display two times normal size characters. The smoothing logic contained in the on-screen display circuit improves the appearance of larger fonts. Fringing circuitry can be activated to improve the visibiity of text by surrounding the character lines with a one-pixel border. RGB outputs provide the direct video signals, and a blanking output is provided to control the video multiplexor. Dot clock and verticle line synchronization are normally obtained from H_FLYBACK and V_FLYBACK, but can be generated by the Z89303/05/047, and driven to the external deflection unit through the bidirectional SYNC ports when external video synchronization signals are not present. User control can be monitored through the keypad port, or the 16-bit remote control capture register. functions such as color and volume can be controlled by eight 8-bit pulse width modulated scanning Receiver directly ports.
All nine PWM ports are available in the 52-pin package. The Z89303/05/07 has two internal 12 MHz VCOs that are referenced to a 32 KHz internal oscillator to provide the system clock. In Sleep mode, the controller uses the 32 KHz clock for the system clock to reduce power consumption. The processor can be suspended by placing it into STOP mode when main power is not available for minimal power consumption.
DC-4222-03
(10-10-94)
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PRELIMINARY
Z89303/05/07 CPS DC-4222-03
GENERAL DESCRIPTION (Continued)
Capture IRIN ADC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0A Port 0B Port 0C Port 0D Port 0E Port 0F Control XTAL1 XTAL2 LPF HSYNC VSYNC /Reset CPU RAM 640 x 16
Address ROM Addr Data
PWM PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 Port1 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Port 19
Port 17 Port 00
Note: Shaded pin functions not available on 40-pin device.
Register Addr/Data
OSD V1 V2 V3 BLANK HALFBLNK ROM 12K x 16 16K x 16 24K x 16
Port0F
ROM Data
Note: Z89307 has 12K words of ROM. Z89305 has 16K words. Z89302/03 has 24K words.
Functional Block Diagram
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PRELIMINARY
Z89303/05/07 CPS DC-4222-03
PWM9 IRIN Port18/G<0> Port19 Port0E Port00/ADC2 Port01/I2SSC Port02/I2SSD Port03 GND Port04/ADC4 Port05/ADC3 Port06/Counter Port07/CSync Port08/R<1> Port09 VCC Port10/R<0> Port11/I2MSC Port12/I2MSD Port13/G<1> Port14/B<0> Port15/B<1> Port16/SCLK Port0A Port0B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Z89303 Z89305 Z89307 52-Pin Shrink DIP
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
PWM8 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 ADC5 CVI/ADC0 LPF XTAL2 AN GND XTAL1 AN VCC /Reset Port0F/HalfBlnk Port17/ADC1 Blank V1 V2 V3 VSync HSync Port0D Port0C
52-Pin Shrink DIP Configuration
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PRELIMINARY
Z89303/05/07 CPS DC-4222-03
PIN DESCRIPTIONS Z89303/05/07
Pin Name VCC - GND - IRIN ADC[5:0] a PWM10, PWM9 PWM[8:1]c Port0[F:0]d Z89303/05/07 52-Pin 17,38 10,40 2 44,11,12,6,35,43 -,1 I nAI OD Configuration Direction Reset PWR PWR I I O
Function +5 V 0V Infrared Remote Capture Input 4-Bit Analog to Digital Converter Input b 14-Bit Pulse Width Modulator Output 8-Bit Pulse Width Modulator Output Bit Programmable Input/Output Ports Bit Programmable Input/Output Ports 12C Clock I/O 12C Data I/O Crystal Oscillator Input Crystal Oscillator Output Loop Filter H_Sync V_Sync Device Reset
Port1[9:0] c SCLf SCD g XTAL1 XTAL2 LPF HSYNC VSYNC /RESET
52,51,50,49, 48,47,46,45 36,5,28,27,26,25, 16,15,14,13,12, 11,9,8,7,6 4,3,35,24,23,22, 21,20,19,18 7 or 19 8 or 20 39 41 42 29 30 37 31,32,33 34 36 23,22,21, 18,15,3 24
OD B
O I
B BOD BOD AI AO AB B B I O O O O O
I
I O O I I I O O
V[3:1] OSD Video Output (Typically Drive B, G, and R Outputs) Blank OSD Blank Output Half Blankh RGB Digital Outputs i SCLKk OSD Half Blank Output R[1:0],G[1:0], and B[1:0] Outputs of the RGB Matrix Internal Processor SCLK
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PRELIMINARY
Z89303/05/07 CPS DC-4222-03
V1, V2, V3 ANALOG OUTPUT Specifications VCC = 5.25 V
VCC = 5.25 V Output Voltage Condition Bit = 11 Bit = 10 Bit = 01 Bit = 00 Settling Time 70% of DC Level, 10pf Load Limit 4.55 V +/- 0.25 V 3.205V +/- 0.2 V 1.95 V +/- 0.15 V 0.65 V +/- 0.1 V < 50 nsec
V1, V2, V3 ANALOG OUTPUT Specifications VCC = 4.75V
VCC = 4.75V Output Voltage Condition Bit = 11 Bit = 10 Bit = 01 Bit = 00 Settling Time 70% of DC Level, 10pf Load Limit 3.90 V +/- 0.25 V 2.90 V +/- 0.2 V 1.90 V +/- 0.15 V 0.1 V +/- 0.1 V < 50 nsec
Z893XX
32K Oscillator Recommended Circuit
Notes: c) PWM[8,7] is not available on the 40-pin DIP version. d) Port0[F:A] is not available on the 40-pin DIP version. e) Port19 is not available on the 40-pin DIP version. f) SCL I/O pin is shared with Port0 or Port11. g) SCD I/O pin is shared with Port02 or Port12. h) Half Blank output is a function shared with Port0F. Half Blank output is not available on the 40-pin DIP version. i) Digital RGB outputs and the internal SCLK are shared with Port1[5:0]. k) Internal processor SCLK is shared with Port16.
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PRELIMINARY
Z89303/05/07 CPS DC-4222-03
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VID VIA VO VO IOH IOH IOL IOL TA TA Parameter Power Supply Voltage Input Voltage Input Voltage Output Voltage Output Voltage Output Output Output Output Current Current Current Current High High Low Low 0 -65 Min 0 -0.3 -0.3 -0.3 -0.3 Max 7 VCC +0.3 VCC +0.3 VCC +0.3 VCC +8.0 -10 -100 20 200 70 150 Units V V V V V mA mA mA mA C C Conditions Digital Inputs Analog Inputs (A/D0...A/D4) All Push-Pull Digital Output Open-Drain PWM Outputs (PWM1...PWM8) One Pin All Pins One Pin All Pins
Operating Temperature Storage Temperature
DC CHARACTERISTICS TA = 0C to + 70C; V CC = 4.5 V to + 5.5 V; FOSC = 32.768 KHz
Symbol VIL VIH VPU VOL VOL VXL VXH VHY IIR IIL ICC ICC1E ICC1 ICC2 Parameter Input Voltage Low Input Voltage High Max. Pull-Up Voltage Output Voltage Low Output Voltage High Input Voltage XTAL1 Low Input Voltage XTAL1 High Schmitt Hysteresis Reset Input Current Input Leakage Supply Current Supply Current of the OTP Supply Current Supply Current Min 0 0.6 VCC Max 0.2 VCC VCC 12 0.4 V CC -0.9 0.3 VCC VCC -2.0 3.0 -3.0 0.75 150 3.0 100 700 300 10 Typical 0.4 3.6 0.16 4.75 1.0 3.5 0.5 90 0.01 60 300 100 5 Units V V V V V V V V A A mA A A A PWM0...PWM8 Only @ IOL = 1 mA @ IOL = 0.75 mA External Clock Generator Driven On XTAL1 Input Pin VRL = 0 V @ 0 V and VCC Sleep Mode @ 32 KHz Sleep Mode @ 32 KHz Sleep Mode Conditions
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PRELIMINARY
Z89303/05/07 CPS DC-4222-03
AC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz
Symbol T PC T RC,TFC T DPOR Parameter Input Clock Period Clock Input Rise and Fall Power On Reset Delay Min 16 0.8 Max 100 Typical 32 12 1.2 Units S S s
AC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz
Symbol TWRES TD HS TDVS TD ES T DOS TWHVS Parameter Power-On Reset Min. Width H_Sync Incoming Signal Width V_Sync Incoming Signal Width Time Delay Between Leading Edge of V_Sync and H_Sync in Even Field Time Delay Between Leading Edge of H_Sync in Odd Field H_Sync/V_Sync Edge Width Min 5.5 0.15 -12 20 Max 5TPC 12.5 1.5 +12 44 2.0 Typical 11 1.0 0 32 0.5 Units S S mS S S S
Notes: All timing of the I 2C bus interface are defined by related specifications of the I 2C bus interface.
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PRELIMINARY
Z89303/05/07 CPS DC-4222-03
Development Projects: Customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems
and delays. No production release is authorized or committed until the Customer and Zilog have agreed upon a Customer Procurement Specification for this project.
Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-con-
formance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues.
(c) 1994 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056
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